Bengaluru-based startup Maieutic Semiconductor is employing artificial intelligence to automate the complex process of analog chip design through a digital assistant for engineers, aiming to accelerate the development of the hardware underpinning much of artificial intelligence (AI), Nikkei Asia reported today.
Maieutic secures $6 mn seed funding
The company has raised $6 million in seed funding, backed by Japan’s University of Tokyo Edge Capital Partners (UTEC) and Indian venture capital firms Endiya Partners and Exfinity Venture Partners.
Maieutic chief executive Gireesh Rajendran, who previously worked at Texas Instruments and Qualcomm, said the company intends to begin early customer trials of its generative AI-powered virtual assistant by March, with a broader commercial rollout to follow.
Rajendran added that the initial phase will target global chipmakers with design centres in India and Japanese semiconductor companies. Maieutic is already in talks with several potential clients interested in adopting the technology.
AI to simplify analog chip design
While design work for digital chips – responsible for processing data and logic in binary form – has been largely automated for decades through electronic design automation (EDA) software, analog and mixed-signal chip design remains heavily manual. US firms such as Synopsys, Cadence Design Systems and Siemens EDA dominate the digital EDA software market, enabling engineers to scale and reuse designs for central processing units and memory devices.
In contrast, analog and mixed-signal chips, which process continuous signals like sound, light and temperature, require expert engineers to fine-tune transistor-level behaviour to ensure circuits handle real-world data accurately.
AI copilot to support engineers
According to Ashish Lachhwani, Maieutic’s chief business officer, Maieutic’s AI copilot acts as an intelligent assistant that integrates with existing design tools. Trained on publicly available data, including patents and research papers, the system can interpret specifications, circuit diagrams and simulation outputs, and respond to engineers’ queries in natural language.
The software can also propose alternative architectures, analyse trade-offs between power efficiency and performance, and automatically review designs to flag inconsistencies. Maieutic estimates that its AI tool could reduce portions of the analog design cycle by 50 to 66 per cent. Users will also be able to run the system locally to ensure data privacy.
